1. Field
Advancements in integrated circuit design, including device density and clock skew in a Computer Aided Design (CAD) context, are needed to provide improvements in performance, efficiency, and utility of use.
2. Related Art
Unless expressly identified as being publicly or well known, mention herein of techniques and concepts, including for context, definitions, or comparison purposes, should not be construed as an admission that such techniques and concepts are previously publicly known or otherwise part of the prior art. All references cited herein (if any), including patents, patent applications, and publications, are hereby incorporated by reference in their entireties, whether specifically incorporated or not, for all purposes. Nothing herein is to be construed as an admission that any of the references are pertinent prior art, nor does it constitute any admission as to the contents or date of actual publication of these documents.
Use of ASICs (application specific integrated circuits) has become widespread in the semiconductor industry as giving circuit design engineers a relatively high amount of functionality in a relatively small package. In particular, ASICs are customizable integrated circuits that are customized in part to implement a circuit specified by a design engineer. The term “ASIC” actually refers to a variety of integrated circuit (IC) styles that vary in degree of customizability, including standard cells, gate arrays, structured ASICs, and FPGAs. As a general rule, the more customization that is required, the more expensive the ASIC will be and the longer the ASIC will take to fabricate.
In forming ASICs generally, several layers will be required. FIG. 1 shows a partial cross-sectional view of a generic integrated circuit. First, active layers 110 are formed on semiconductor substrate. The active layers 110 include devices such as transistors and diodes. Many active layer devices are formed independently of one another, i.e., they are not yet connected to other devices. Thus, once active layers 110 are formed, additional conducting layers, which are often composed of a metal such as aluminum or copper, are formed over the active layers to further interconnect the devices. Several conducting layers may be required to completely interconnect the devices to form a useful circuit. Four conducting layers, M1 120, M2 130, M3 140, and M4 150, are shown in FIG. 1. Of course, different types of ICs or ICs fabricated using different processes may require more or less than four metal layers for circuit interconnection.
In between each conducting layer is an insulating layer 115, 125, 135, 145 as shown in FIG. 1. Insulating layers are present to provide electrical isolation and mechanical spacing between conducting layers. To interconnect the conducting layers, vias 116 are formed through the insulating layers and are filled with conducting material (e.g., a metal or metal silicide).
In forming the structure of FIG. 1, after the active layers 110 are formed, an insulating layer 115 is formed over the active layers 110, for instance, by growth or deposition of insulating material. Next, a masking step is utilized to form vias in the insulating layer, as is generally known in the art. Such masking often entails depositing a photoresist layer and patterning the layer using ultra-violet light, enabling removal of only selected portions of the photoresist, and then etching the insulating layer in accordance with the photoresist pattern. After forming the vias, a conducting layer is deposited and then patterned using a similar masking process, so that metal (or other conductor such as a metal silicide) remains only in desired locations. The process is repeated for each insulating layer and conducting layer required to be formed. Thus each conducting layer required to be formed generally demands at least two masking steps: one step to form vias through the insulating layer to connect to the layer below and one step to form connection wires or lines.
Referring to FIG. 2a, at the active layer level, ASIC active devices are generally grouped to form function blocks 210, also commonly referred to as “cells” or “modules.” The function blocks 210 are arranged to form an array 200. In particular, in structured ASICs the active devices within function blocks are interconnected (using one or more conducting layers) to form predefined function block circuits. As a simple example, such a function block circuit may include one or more multiplexers, as shown in FIG. 2b. Other more complicated function block circuits can include both combinational circuitry (e.g., Boolean logic and multiplexers) as well as sequential circuitry. (e.g., latches and flip-flops), as shown in FIG. 2c. Frequently, each function block in the array is identical to the rest. However, some structured ASICs have more than one type of function block.
In structured ASICs array 200 is sometimes loosely referred to as the “base array” because the predefined function blocks 210 correspond to lower fabrication layers that act as a foundation (or base) for the higher customization layers. However, as used hereinafter, “base array” more specifically means those layers of a structured ASIC that are adapted to be prefabricated. The number and type of layers adapted to be prefabricated in the base array will vary by embodiment.
Each function block circuit can generally be configured to perform a selected logic function by controlling the inputs to the function block, e.g., coupling the inputs to power, ground, an I/O pad, or to the output of another function block. Hence, to customize a structured ASIC to implement an ad hoc circuit design defined by a user, routing between the function blocks (and sometimes within the function blocks) must be customized. Typically, these custom conducting layers are the top metal layers for the device, enabling the base array of the structured ASIC to be prefabricated prior to receiving an ad hoc circuit design from a user, thus further enabling rapid customization time.
In addition to routing amongst function blocks, customized routing in structured ASICs generally includes defining and routing clock resources. In particular, custom routing resources are frequently used to build “clock trees” which drive clock inputs to sequential elements like flip-flops and latches. Nonetheless, the majority of custom routing for structured ASICs is performed automatically by place and route software. Yet such automatic place and route of clock resources does not typically yield optimal clock skew because buffers and routes for clock trees cannot always be optimally placed and routed due to competition for resources with other (non-clock) parts of the circuit. Manual placement of clock routing resources is simply undesirable.
Moreover, the electronics industry continues to demand smaller devices. Hence any structured ASIC that can maintain the same functionality but in a smaller package to that done currently (or the same size package with additional functionality) would be desirable.